In most pipelined microprocessor architectures, one of the final stages in the pipeline is committing of instructions. Various committing techniques are known in the art. For example, Cristal et al. describe processor microarchitectures that allow for committing instructions out-of-order, in “Out-of-Order Commit Processors,” IEE Proceedings—Software, February, 2004, pages 48-59, which is incorporated herein by reference.
Ubal et al. evaluate the impact of retiring instructions out of order on different multithreaded architectures and different instruction-fetch policies, in “The Impact of Out-of-Order Commit in Coarse-Grain, Fine-Grain and Simultaneous Multithreaded Architectures,” IEEE International Symposium on Parallel and Distributed Processing, April, 2008, pages 1-11, which is incorporated herein by reference.
Some suggested techniques enable out-of-order committing of instructions using checkpoints. Checkpoint-based schemes are described, for example, by Akkary et al., in “Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors,” Proceedings of the 36th International Symposium on Microarchitecture, 2003; and by Akkary et al., in “Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers,” IEEE Micro, volume 23, issue 6, November, 2003, Pages 11-19, which are incorporated herein by reference.